Early Results Using Hardware Transactional Memory for High-Performance Computing Applications

Transactional memory (TM) is a novel approach for handling concurrency issues. By experimenting on a prototype system implementing transactional memory in hardware, we aim at investigating if TM is of benefit for scientific and high-performance computing. The main goal of our work is to exploit the optimistic nature of transactional memory and increase performance by reducing the overhead from locks and thread synchronization. Preliminary results are presented for a basic particle dynamics computation, which is one of the most widely used HPC algorithms. We show that using hardware transactional memory gives a performance improvement over corresponding implementations using locks, which can be as big as a factor of two for the extreme cases.